Double-Gate Tunnel FET With High-κ Gate Dielectric

In this paper, we propose and validate a novel design for a double-gate tunnel fi eld-effect transistor (DG Tunnel FET), for which the simulations show significant improvements compared with single-gate devices using an SiO2 gate dielectric. For the fi rst time, DG Tunnel FET devices, which are using a high-κ gate dielectric, are explored using realistic design parameters, showing an ON-current as high as 0.23 mA for a gate voltage of 1.8 V, an OFF-current of less than 1 fA (neglecting gate leakage), an improved average subthreshold swing of 57 mV/dec, and a minimum point slope of 11 mV/dec. The 2-D nature of Tunnel FET current fl ow is studied, demonstrating that the current is not confi ned to a channel at the gate-dielectric surface. When varying temperature, Tunnel FETs with a high-κ gate dielectric have a smaller threshold voltage shift than those using SiO2, while the subthreshold slope for fi xed values of Vg remains nearly unchanged, in contrast with the traditional MOSFET. Moreover, an Ion/Ioff ratio of more than 2 × 1011 is shown for simulated devices with a gate length (over the intrinsic region) of 50 nm, which indicates that the Tunnel FET is a promising candidate to achieve better-than-ITRS low-standby-power switch performance.